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Making Your Code Run Faster: Hardware… duration 3 minutes 2 seconds Making Your Code Run Faster: Hardware… Making Your Code Run Faster: Hardware Acceleration for Similar Input Data, Haiyue Ma, GS (2924007)	Making Your Code Run Faster: Hardware Acceleration for Similar Input Data, Haiyue Ma, GS (2924007) It is crucial to make computer programs run faster. Traditionally, the execution time for the same program stays the same regardless of the inputs. Based on the observation that programs tend to… prd23 princeton research day graduate research electrical and computer engineering design and engineering input values images computer inputs fact cache advantage presentation similarity lot axis shift computers application applications access thing harvard contexts From Research Princeton Research Day 0 likes 105 plays Date May 4th, 2023 Speaker Haiyue Ma, GS Department Electrical and Computer Engineering
What's next after the End of Moore's… duration 3 minutes 27 seconds What's next after the End of Moore's… What's next after the End of Moore's Law, Marcelo Orenes Vera, G3 (3964916)	What's next after the End of Moore's Law, Marcelo Orenes Vera, G3 (3964916) Moore's law is a prediction made by the president of Intel in 1965, Gordon Moore, who predicted that the number of transistors per circuit would double every 18 to 24 months. This trend was a… memory programmer obligations chip transistor access hardware moore compiler isa catches model instructions programming cache accelerators parallelism performance scaling dennard From Research Princeton Research Day 5 likes 50 plays Date April 27th, 2022 Speaker Marcelo Orenes Vera Department Computer Science
Shuwen Deng 03.21.2022 Job Talk P.1 duration 1 hour 8 minutes Shuwen Deng 03.21.2022 Job Talk P.1 Shuwen Deng 03.21.2022 Job Talk P.1	Shuwen Deng 03.21.2022 Job Talk P.1 step attacks cache side model attack channel memory tlb cash attacker abilities timing processor question vulnerabilities microarchitectures access end victim From Broadcast Broadcast Center Staff 0 likes 62 plays
Unifying Caching Objectives with Learning Relaxed… duration 4 minutes 58 seconds Unifying Caching Objectives with Learning Relaxed… Unifying Caching Objectives with Learning Relaxed Belady	Unifying Caching Objectives with Learning Relaxed Belady Caching is crucial to the end-to-end performance of distributed systems. By storing content that is commonly requested so that it can be served faster, this technique can improve request latency and… prd20 objects ratio object size objectives cache algorithm art access requests performance caching workloads unit byte times miss bins eviction hyperparameter From Research Princeton Research Day 0 likes 7 plays Date April 29th, 2020 Speaker Audrey Cheng '20 Department Computer Science
Unifying Caching Objectives with Learning Relaxed… duration 4 minutes 58 seconds Unifying Caching Objectives with Learning Relaxed… Unifying Caching Objectives with Learning Relaxed Belady	Unifying Caching Objectives with Learning Relaxed Belady Caching is crucial to the end-to-end performance of distributed systems. By storing content that is commonly requested so that it can be served faster, this technique can improve request latency and… prd20 objects ratio object size objectives cache algorithm art access requests performance caching workloads unit byte times miss bins eviction hyperparameter From Research Princeton Research Day 0 likes 30 plays Date April 29th, 2020 Speaker Audrey Cheng '20 Department Computer Science